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november 2009 doc id 10522 rev 9 1/42 1 stm690a, stm692a, stm703 stm704, stm802, stm805, stm817/8/9 5 v supervisor with battery switchover features 5 v operating voltage nvram supervisor for external lpsram chip-enable gating (stm818 only) for external lpsram (7 ns max prop delay) rst and rst outputs 200 ms (typ) t rec watchdog timer - 1.6 sec (typ) automatic battery switchover low battery supply current - 0.4 a (typ) power-fail comparator (pfi/pfo ) low supply current - 40 a (typ) guaranteed rst (rst) assertion down to v cc = 1.0 v operating temperature: ?40 c to +85 c (industrial grade) rohs compliance ? lead-free components are compliant with the rohs directive. 1. contact local st sales office for availability. 8 1 tssop8 3 x 3 (ds) (1) so8 (m) table 1. device summary part number watchdog input active-low rst (1) active- high rst manual reset input (1) battery switch- over power-fail comparator chip- enable gating battery freshness seal stm690a ?? ?? stm692a ?? ?? stm703 ???? stm704 ???? stm802l/m ?? ?? stm805l ???? stm817l/m ?? ?? ? stm818l/m ?? ? ?? stm819l/m ???? ? 1. all rst and rst outputs are push-pull. www.st.com
contents stm690a/692a/703 /704/802/805/817/818/819 2/42 doc id 10522 rev 9 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.1 mr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.2 wdi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.3 rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.4 rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.5 v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.6 v bat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.7 e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.8 e con . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.9 pfi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.10 pfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 push-button reset input (stm703/704/819) . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 watchdog input (not available on stm703/704/819) . . . . . . . . . . . . . . . 13 2.4 backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 chip-enable gating (stm818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 chip-enable input (stm818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 chip-enable output (stm818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8 power-fail input/output (not available on stm818) . . . . . . . . . . . . . . . . 16 2.9 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10 using a supercap? as a backup power source . . . . . . . . . . . . . . . . . . . 17 2.11 negative-going v cc transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.12 battery freshness seal (stm817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . 18 3 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
stm690a/692a/703/704/802/ 805/817/818/819 contents doc id 10522 rev 9 3/42 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
list of tables stm690a/692a /703/704/802/80 5/817/818/819 4/42 doc id 10522 rev 9 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. i/o status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 6. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7. dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. so8 - 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . 37 table 9. tssop8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 38 table 10. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 11. marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
stm690a/692a/703/704/802/805/ 817/818/819 list of figures doc id 10522 rev 9 5/42 list of figures figure 1. logic diagram (stm690a/692/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram (stm703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. logic diagram (stm818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. stm690a/692a/802/805/817 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. stm703/704/819 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6. stm818 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. block diagram (stm690a/692a/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. block diagram (stm703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 figure 9. block diagram (stm818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. chip-enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 12. chip-enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 13. power-fail comparator waveform (stm817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 14. power-fail comparator waveform (stm690a/692a/703/704/802/805) . . . . . . . . . . . . . . . . 17 figure 15. using a supercap? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 16. freshness seal enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 17. v cc to v out on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 18. v bat to v out on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 19. supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 figure 20. battery current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 21. v pfi threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 22. reset comparator propagation delay vs. temperature (other than stm817/818/819) . . . . 21 figure 23. reset comparator propagation delay vs. temperature (v bat = 3.0 v; stm817/818/819) . 22 figure 24. power-up t rec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 25. normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 26. watchdog time-out period vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 27. e to e con on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 28. pfi to pfo propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 29. output voltage vs. load current (v cc = 5 v; v bat = 2.8 v; t a = 25 c) . . . . . . . . . . . . . . . 25 figure 30. output voltage vs. load current (v cc = 0 v; v bat = 2.8 v; t a = 25 c) . . . . . . . . . . . . . . . 25 figure 31. rst output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 32. rst output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 33. rst response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 34. rst response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 35. power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 36. power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 37. maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 38. e to e con propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 39. e to e con propagation delay test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 40. ac testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 41. mr timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 42. watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 43. so8 - 8-lead plastic small outline, 150 mils body width, package mechanical drawing . . . 37 figure 44. tssop8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, outline . . . . . . . . . . . . . . 38
description stm690a/692a/ 703/704/802/805/817/818/819 6/42 doc id 10522 rev 9 1 description the stm690a/692a/703/704/802/805/817/818/819 supervisors are self-contained devices which provide microprocessor supervisory func tions with the ability to non-volatize and write-protect external lpsram. a precision voltage reference and comparator monitors the v cc input for an out-of-tolerance condition. when an invalid v cc condition occurs, the reset output (rst ) is forced low (or high in the case of rst). these devices also offer a watchdog timer (except for stm703/704/819) as well as a power-fail comparator (except for stm818) to provide the system with an early warning of impending power failure. these devices are available in a standard 8-pin soic package or a space-saving 8-pin tssop package. figure 1. logic diagram (stm690a/692/802/805/817) 1. for stm805, reset output is active-high. figure 2. logic diagram (stm703/704/819) ai07 8 94 v cc v bat s tm690a/ 692a/ 8 02/ 8 05/ 8 17 v ss v out r s t(r s t) (1) wdi pfi pfo ai07 8 95 v cc v bat s tm70 3 / 704/ 8 19 v ss v out r s t mr pfi pfo
stm690a/692a/703/704/802/80 5/817/818/819 description doc id 10522 rev 9 7/42 figure 3. logic diagram (stm818) figure 4. stm690a/692a/802/805/817 connections 1. for stm805, reset output is active-high. table 2. signal names mr push-button reset input wdi watchdog input rst active-low reset output rst active-high reset outpu e (1) 1. stm818 chip-enable input e con (1) conditioned chip-enable output v out supply voltage output v cc supply voltage v bat backup supply voltage pfi power-fail input pfo power-fail output v ss ground ai07 8 96 v cc v bat s tm 8 1 8 v ss v out r s t wdi e e con 1 pfo pfi wdi r s t(r s t) (1) v cc v out v bat v ss ai07 88 9 s o 8 /t ss op 8 2 3 4 8 7 6 5
description stm690a/692a/ 703/704/802/805/817/818/819 8/42 doc id 10522 rev 9 figure 5. stm703/704/819 connections figure 6. stm818 connections 1.1 pin descriptions 1.1.1 mr a logic low on mr asserts the reset output. reset remains asserted as long as mr is low and for t rec after mr returns high. this active-low input has an internal pull-up. it can be driven from a ttl or cmos logic line, or shorted to ground with a switch. leave open if unused. 1.1.2 wdi if wdi remains high or low for 1.6 sec, the internal watchdog timer runs out and reset is triggered. the internal watchdog timer clears while reset is asserted or when wdi sees a rising or falling edge. the watchdog function can be disabled by allowing the wdi pin to float. 1.1.3 rst pulses low for t rec when triggered, and stays low whenever v cc is below the reset threshold or when mr is a logic low. it remains low for t rec after either v cc rises above the reset threshold, the watchdog triggers a reset, or mr goes from low to high. 1.1.4 rst pulses high for t rec when triggered, and stays high whenever v cc is above the reset threshold or when mr is a logic high. it remains high for t rec after either v cc falls below the reset threshold, the watchdog triggers a reset, or mr goes from high to low. 1 pfo pfi mr r s t v cc v out v bat v ss ai07 8 90 s o 8 /t ss op 8 2 3 4 8 7 6 5 1 e con e wdi r s t v cc v out v bat v ss ai07 8 92 s o 8 /t ss op 8 2 3 4 8 7 6 5
stm690a/692a/703/704/802/80 5/817/818/819 description doc id 10522 rev 9 9/42 1.1.5 v out when v cc is above the switchover voltage (v so ), v out is connected to v cc through a p- channel mosfet switch. when v cc falls below v so , v bat connects to v out . 1.1.6 v bat when v cc falls below v so , v out switches from v cc to v bat . when v cc rises above v so + hysteresis, v out reconnects to v cc . v bat may exceed v cc . connect to v cc if no battery is used. 1.1.7 e the input to the chip-enable gating circuit. connect to ground if unused. 1.1.8 e con e con goes low only when e is low and reset is not asserted. if e con is low when reset is asserted, e con will remain low for 15 s or until e goes high, whichever occurs first. in the disabled mode, e con is pulled up to v out . 1.1.9 pfi when pfi is less than v pfi or when v cc falls below 2.4 v (or v so ), pfo goes low; otherwise, pfo remains high. connect to ground if unused. 1.1.10 pfo when pfi is less than v pfi , or v cc falls below 2.4 v (or v so ), pfo goes low; otherwise, pfo remains high. leave open if unused. output type is push-pull.
description stm690a/692a/ 703/704/802/805/817/818/819 10/42 doc id 10522 rev 9 figure 7. block diagram (s tm690a/692a/802/805/817) 1. for stm805, reset output is active-high. table 3. pin description pin name function stm818 stm690a stm692a stm802 stm817 stm703 stm704 stm819 stm805 --6-mr push-button reset input 6 6 - 6 wdi watchdog input 777 -rst active-low reset output - - - 7 rst active-high reset output 1111v out supply output for external lpsram 2222v cc supply voltage 8888v bat backup battery input 4- - -e chip-enable input 5- - -e con conditioned chip-enable output - 4 4 4 pfi power-fail input -555pfo power-fail output (push-pull) 3333v ss ground ai07 8 97 watchdog timer v r s t v out compare compare compare t rec gener a tor v pfi v bat v s o v cc pfi wdi r s t(r s t) (1) pfo
stm690a/692a/703/704/802/80 5/817/818/819 description doc id 10522 rev 9 11/42 figure 8. block diagram (stm703/704/819) figure 9. block diagram (stm818) ai07 8 9 8 v r s t v out compare compare compare t rec gener a tor v pfi v bat v s o v cc pfi mr r s t pfo ai07 8 99 a watchdog timer v r s t v out e con compare compare t rec gener a tor e con output control v bat v s o v cc wdi r s t e
description stm690a/692a/ 703/704/802/805/817/818/819 12/42 doc id 10522 rev 9 figure 10. hardware hookup 1. for stm690a/692a/802/805/817/818. 2. for stm818 only. 3. not available on stm818. 4. for stm703/704/819. 5. active high on stm805. e v cc ai07 8 9 3 v cc e con (2) mr (4) v out e v cc lp s ram pfi ( 3 ) 0.1 f 0.1 f s tm690a/692a/ 70 3 /704/ 8 02/ 8 05/ 8 17/ 8 1 8 / 8 19 wdi (1) pfo ( 3 ) r s t to microproce ss or re s et unreg u l a ted volt a ge reg u l a tor v cc v in r1 r2 p us h-b u tton from microproce ss or e (2) v bat to microproce ss or nmi (5)
stm690a/692a/703/704/802/ 805/817/818/819 operation doc id 10522 rev 9 13/42 2 operation 2.1 reset output the stm690a/692a/703/704/802/805/817/818/819 supervisor asserts a reset signal to the mcu whenever v cc goes below the reset threshold (v rst) , a watchdog time-out occurs, or when the push-button reset input (mr ) is taken low. rst is guaranteed to be a logic low (logic high for stm805) for 0v < v cc < v rst if v bat is greater than 1 v. without a backup battery, rst is guaranteed valid down to v cc =1 v. during power-up, once v cc exceeds the reset threshold an internal timer keeps rst low for the reset time-out period, t rec . after this interval rst returns high. if v cc drops below the reset threshold, rst goes low. each time rst is asserted, it stays low for at least the reset time-out period (t rec ). any time v cc goes below the reset threshold the internal timer clears. the reset timer starts when v cc returns above the reset threshold. 2.2 push-button reset input (stm703/704/819) a logic low on mr asserts reset. reset remains asserted while mr is low, and for t rec (see figure 41 ) after it returns high. the mr input has an internal 40 k pull-up resistor, allowing it to be left open if not used . this input can be driven wit h ttl/cmos-logic levels or with open-drain/collector outputs. connect a normally open momentary switch from mr to gnd to create a manual reset function; external debounce circuitry is not required. if mr is driven from long cables or the device is used in a noisy environment, connect a 0.1 f capacitor from mr to gnd to provide additional noise immunity. mr may float, or be tied to v cc when not used. 2.3 watchdog input (not a vailable on stm703/704/819) the watchdog timer can be used to detect an out-of-control mcu. if the mcu does not toggle the watchdog input (wdi) within t wd (1.6 sec typ), the reset is asserted. the internal watchdog timer is cleared by either: 1. a reset pulse, or 2. by toggling wdi (high-to-low or low-to-high), which can detect pulses as short as 50ns. if wdi is tied high or low, a reset pulse is triggered every 1.8 sec (t wd + t rec ). the timer remains cleared and does not count for as long as reset is asserted. as soon as reset is released, the timer starts counting (see figure 42 ). note: 1 the watchdog function may be disabled by fl oating wdi or tri-stating the driver connected to wdi. when tri-stated or disconnected, the maxi mum allowable leakage current is 10 a and the maximum allowable load capacitance is 200 pf. 2 input pulses less than 20 ns will be ignored.
operation stm690a/692a/703/704/802/805/817/818/819 14/42 doc id 10522 rev 9 2.4 backup battery switchover in the event of a power failure, it may be necessary to preserve the contents of external sram through v out . with a backup battery installed with voltage v bat , the devices automatically switch the sram to the backup supply when v cc falls. note: if backup battery is not used, connect both v bat and v out to v cc . whenever v cc falls below the switchover voltage, v so , v out is connected to v bat through a 100 switch. v so is the lesser of v bat and v rst . choosing the lesser allows the device to be powered by v cc for as long as possible before switching over thereby maximizing the battery life. assuming v bat > 2.0 v, switchover at v so ensures that battery backup mode is entered before v out gets too close to the 2.0 v minimum required to reliably retain data in most external srams. when v cc recovers, hysteresis is used to avoid oscillation around the v so point. v out is connected to v cc through a 3 pmos power switch. note: the backup battery may be removed while v cc is valid, assuming v bat is adequately decoupled (0.1 f ty p), without danger of triggering a reset. 2.5 chip-enable gating (stm818 only) internal gating of the chip-enable (e ) signal prevents erroneous data from corrupting the external cmos ram in the event of an undervoltage condition. the stm818 uses a series transmission gate from e to e con (see figure 11 ). during normal operation (reset not asserted), the e transmission gate is enabled and passes all e transitions. when reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the cmos ram. the short propagation delay from e to e con enables the stm818 to be used with most ps. if e is low when reset asserts, e con remains low for typically 15 s (or until e goes high) to permit the current write cycle to complete. connect e to v ss if unused. table 4. i/o status in battery backup v out connected to v bat through internal switch v cc disconnected from v out pfi disabled pfo logic low e high impedance e con logic high wdi watchdog timer is disabled mr disabled rst logic low rst logic high v bat connected to v out
stm690a/692a/703/704/802/ 805/817/818/819 operation doc id 10522 rev 9 15/42 2.6 chip-enable input (stm818 only) the chip-enable transmission gate is disabled and e is high impedance (disabled mode) while reset is asserted. during a power-down sequence when v cc passes the reset threshold, the chip-enable transmission gate disables and e immediately becomes high impedance if the voltage at e is high. if e is low when reset asserts, the chip-enable transmission gate will disable 15 s after reset asserts (see figure 12 ). this permits the current write cycle to comp lete during power-down. any time a reset is generated, the chip-enable transmission gate remains disabled and e remains high impedance (regardless of e activity) for the reset time-out period. when the chip-enable transmission gate is enabled, the impedance of e appears as a 40 resistor in series with the load at e con . the propagation delay through the chip-enable transmission gate depends on v cc , the source impedance of the drive connected to e , and the loading on e con . the chip-enable propagation delay is production tested from the 50% point on e to the 50% point on e con using a 50 driver and a 50 pf load capacitance (see figure 39 ). for minimum propagation delay, minimize the capacitive load at e con and use a low-output impedance driver. 2.7 chip-enable outp ut (stm818 only) when the chip-enable transmission gate is enabled, the impedance of e con is equivalent to a 40 resistor in series wit h the source driving e . in the disabled mode, the transmission gate is off and an active pull-up connects e con to v out (see figure 11 ). this pull-up turns off when the transmission gate is enabled. figure 11. chip-enable gating figure 12. chip-enable waveform ai0 88 02 v r s t v out v cc compare e con t rec gener a tor e con output control r s t e ai0 88 0 3b r s t e v cc v r s t v bat e con t rec t rec 15 s xx xx
operation stm690a/692a/703/704/802/805/817/818/819 16/42 doc id 10522 rev 9 2.8 power-fail input/output (not available on stm818) the power-fail input (pfi) is compared to an internal reference voltage (independent from the v rst comparator). if pfi is less than the power-fail threshold (v pfi ), the power-fail output (pfo ) will go low. this function is intended for use as an underv oltage detector to signal a failing power supply. typically pfi is connected through an external voltage divider (see figure 12 ) to either the unregulated dc input (if it is available) or the regulated output of the v cc regulator. the voltage divider can be set up such that the voltage at pfi falls below v pfi several milliseconds before the regulated v cc input to the stm690a/692a/703/704/802/805/817/818/819 supervisor or before the microprocessor drops below the minimum operatin g voltage. this provides several milliseconds of advanced warning that power is about to fail. during battery backup, the power-fail comparator turns off and pfo goes (or remains) low (see figure 13 below and figure 14 ). this occurs after v cc drops below 2.4 v (or v so ). when power returns, pfo is forced high (stm817/819 only), irrespective of v pfi for the write protect time (t rec ). at the end of this time, the power-fail comparator is enabled and pfo follows pfi. if the comparator is unused, pfi should be connected to v ss and pfo left unconnected. pfo may be connected to mr on the stm703/704/818 so that a low voltage on pfi will generate a reset output. 2.9 applications information these supervisor circuits are not s hort-circuit protected. shorting v out to ground - excluding power-up transients such as charging a decoupling capacitor - destroys the device. decouple both v cc and v bat pins to ground by placing 0.1 f capacitors as close to the device as possible. figure 13. power-fail comparator waveform (stm817/818/819) ai0 88 04 a v cc v r s t v s o (or 2.4v) t rec r s t to e con del a y ( s tm 8 1 8 ) r s t e con ( s tm 8 1 8 ) pfo ( s tm 8 17/ 8 19) pfo follow s pfi pfo follow s pfi
stm690a/692a/703/704/802/ 805/817/818/819 operation doc id 10522 rev 9 17/42 figure 14. power-fail comparator wa veform (stm690a/692a/703/704/802/805) 2.10 using a supercap? as a backup power source supercaps? are capacitors with extremely high capacitance values (e.g., 0.47 f) for their size. figure 15 shows how to use a supercap as a backup power source. the supercap may be connected through a diode to the 5 v supply. since v bat can exceed v cc while v cc is above the reset threshold, there are no sp ecial precautions for using these supervisors with a supercap. 2.11 negative-going v cc transients the stm690a/692a/703/704/802/805/817/818/819 supervisors are relatively immune to negative-going v cc transients (glitches). figure 37 shows typical transient duration versus reset comparator overdrive (for which the stm690a/692a/703/704/802/805/817/818/819 will not generate a reset pulse). the graph wa s generated using a ne gative pulse applied to v cc , starting at v rst + 0.3 v and ending below the reset threshold by the magnitude indicated (comparator overdrive). the graph indicates the maximum pulse width a negative v cc transient can have without causing a reset pulse. as the magnitude of the transient increases (further below the threshold), the maximum allowable pulse width decreases. any combination of duration and ov erdrive which lies under the cu rve will not generate a reset signal. typically, a v cc transient that goes 100 mv below the reset threshold and lasts 40 s or less will not cause a reset pulse. a 0.1 f bypass capacitor mounted as clos e as possible to the v cc pin provides additional transient immunity. ai0 883 2 a v cc v r s t 2.4v (or v s o ) t rec r s t pfo pfo follow s pfi pfo follow s pfi
operation stm690a/692a/703/704/802/805/817/818/819 18/42 doc id 10522 rev 9 2.12 battery freshness s eal (stm817/818/819) the battery freshness seal disconnects the backup battery from internal circuitry and v out until it is needed. this allows an oem to ensure that the backup battery connected to v bat will be fresh when the final product is put to use. to enable the freshness seal: 1. connect a battery to v bat 2. ground pfo 3. bring v cc above the reset threshold and hold it there until reset is deasserted following the reset timeout period and 4. bring v cc down again ( figure 16 ) use the same procedure for the stm818, but ground e con instead of pfo . once the battery freshness seal is enabled (disconnecting the backup battery from internal circuitry and anything connected to v out ), it remains enabled until v cc is brought above v rst . figure 15. using a supercap? figure 16. freshness seal enable waveform ai0 88 05 s tmxxx v bat v cc v out 5v gnd r s t to extern a l s ram to p ai08806 rst pfo (stm817/819) v cc v rst e con (stm818) t rec (externally held at 0v) (externally held at 0v) e con out state latched at 1/2 t rec , freshness seal enabled pfo out state latched at 1/2 t rec , freshness seal enabled
stm690a/692a/703/704/802/ 805/817/818/819 typical operating characteristics doc id 10522 rev 9 19/42 3 typical operating characteristics note: typical values are at t a = 25 c. figure 17. v cc to v out on-resistance vs. temperature figure 18. v bat to v out on-resistance vs. temperature 0.0 1.0 2.0 3 .0 4.0 5.0 ?40 ?20 0204060 8 0 100 120 temper a t u re ( c) v cc to v out on-re s i s t a nce ( ) v cc = 3 .0v v cc = 4.5v v cc = 5.5v ai1049 8 temper a t u re ( c) v bat to v out on-re s i s t a nce ( ) ai09140 b 0 20 40 60 8 0 100 120 140 160 ?40 ?20 0 20 40 60 8 0 100 120 v bat = 2.0v v bat = 3 .0v v bat = 3 . 3 v v bat = 3 .6v
typical operating characteristics stm6 90a/692a/703/704/8 02/805/817/818/819 20/42 doc id 10522 rev 9 figure 19. supply current vs. temperature (no load) figure 20. battery current vs. temperature temperature ( c) supply current ( a) ai09141 b 0 5 10 15 20 25 30 ?40 ?20 0 20 40 60 80 100 120 v cc = 2.7v v cc = 3.0v v cc = 3.6v v cc = 4.5v v cc = 5.5v temper a t u re ( c) b a ttery su pply c u rrent (na) 0.1 1 10 100 1000 ?40 ?20 0 20 40 60 8 0 100 120 v bat = 2.0v v bat = 3 .0v v bat = 3 .6v ai10499
stm690a/692a/703/704/802/ 805/817/818/819 typical operating characteristics doc id 10522 rev 9 21/42 figure 21. v pfi threshold vs. temperature figure 22. reset comparator propagation dela y vs. temperature (other than stm817/818/819) temperature ( c) v pfi threshold (v) ai09142c 1.225 1.230 1.235 1.240 1.245 1.250 1.255 1.260 1.265 1.270 ?40 ?20 0 20 40 60 80 100 120 v cc = 3.0v v cc = 4.5v v cc = 4.75v v cc = 5.5v temperature ( c) propagation delay ( s) ai0914 3b 10 12 14 16 18 20 22 24 26 28 30 ?40 ?20 0 20 40 60 80 100 120
typical operating characteristics stm6 90a/692a/703/704/8 02/805/817/818/819 22/42 doc id 10522 rev 9 figure 23. reset comparator propagation delay vs. temperature (v bat = 3.0 v; stm817/818/819) figure 24. power-up t rec vs. temperature temperature ( c) propagation delay ( s) 0 50 100 150 200 250 300 350 ?40 ?20 0 20 40 60 80 100 120 1v/ms 10v/ms ai11100 ai09144 b temperature ( c) t rec (ms) 210 215 220 225 230 235 240 ?40 ?20 0 20 40 60 80 100 120 v cc = 3.0v v cc = 4.5v v cc = 5.5v
stm690a/692a/703/704/802/ 805/817/818/819 typical operating characteristics doc id 10522 rev 9 23/42 figure 25. normalized reset threshold vs. temperature figure 26. watchdog time-out period vs. temperature temperature ( c) normalized reset threshold ai09145 b 0.996 0.998 1.000 1.002 1.004 ?40 ?20 0 20 40 60 80 100 120 temperature ( c) watchdog time-out period (sec) ai09146 b 1.60 1.65 1.70 1.75 1.80 1.85 1.90 ?40 ?20 0 20 40 60 80 100 120 v cc = 3.0v v cc = 4.5v v cc = 5.5v
typical operating characteristics stm6 90a/692a/703/704/8 02/805/817/818/819 24/42 doc id 10522 rev 9 figure 27. e to e con on-resistance vs. temperature figure 28. pfi to pfo propagation delay vs. temperature temperature ( c) e to e con on-resistance ( ) ai09147 b 0 10 20 30 40 50 60 ?40 ?20 0 20 40 60 80 100 120 v cc = 3.0v v cc = 4.5v v cc = 5.5v temperature ( c) ai0914 8b pfi to pfo propagation delay ( s) 0.0 1.0 2.0 3.0 4.0 ?40 ?20 0 20 40 60 80 100 120 v cc = 3.0v v cc = 3.6v v cc = 4.5v v cc = 5.5v
stm690a/692a/703/704/802/ 805/817/818/819 typical operating characteristics doc id 10522 rev 9 25/42 figure 29. output voltage vs. load current (v cc = 5 v; v bat = 2.8 v; t a = 25 c) figure 30. output voltage vs. load current (v cc = 0 v; v bat = 2.8 v; t a = 25 c) 4.94 4.96 4.98 5.00 01020304050 i out (ma) v out (v) ai10496 2.66 2.68 2.70 2.72 2.74 2.76 2.78 2.80 0.0 0.2 0.4 0.6 0.8 1.0 i out (ma) v out (v) ai10497
typical operating characteristics stm6 90a/692a/703/704/8 02/805/817/818/819 26/42 doc id 10522 rev 9 figure 31. rst output voltage vs. supply voltage figure 32. rst output voltage vs. supply voltage v rst (v) v cc (v) ai09149 b 500ms/div v rst v cc 0 1 2 3 4 5 0 1 2 3 4 5 v rst (v) v cc (v) ai09150 b 0 1 2 3 4 5 0 1 2 3 4 5 v rst v cc 500ms/div
stm690a/692a/703/704/802/ 805/817/818/819 typical operating characteristics doc id 10522 rev 9 27/42 figure 33. rst response time (assertion) figure 34. rst response time (assertion) ai09151 b 5v 5v v cc 4v 1v/div 4v 1v/div 0v 5 s /div r s t ai09152 b v cc 4v 5v 1v/div 4v 1v/div 0v 5s/div rst
typical operating characteristics stm6 90a/692a/703/704/8 02/805/817/818/819 28/42 doc id 10522 rev 9 figure 35. power-fail comparator response time (assertion) figure 36. power-fail comparator response time (de-assertion) 5v 1.3v pfi 1v/div 0v 500mv/div 0v 500ns/div ai0915 3b pfo ai09154 b 5v 1.3v pfi 1v/div 0v 500mv/div 0v 500ns/div pfo
stm690a/692a/703/704/802/ 805/817/818/819 typical operating characteristics doc id 10522 rev 9 29/42 figure 37. maximum transient duration vs. reset threshold overdrive figure 38. e to e con propagation delay vs. temperature reset comparator overdrive, v rst ? v cc (v) reset occurs above the curve. transient duration ( s) ai09156 b 0 1000 2000 3000 4000 5000 6000 0 1 1 1 . 0 1 0 . 0 1 0 0 . 0 temperature ( c) e to e con propagation delay (ns) ai09157 b 0.0 1.0 2.0 3.0 4.0 ?40 ?20 0 20 40 60 80 100 120 v cc = 3.0v v cc = 4.5v v cc = 5.5v
maximum ratings stm 690a/692a/703/704/802/805/817/818/819 30/42 doc id 10522 rev 9 4 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 5. absolute maximum ratings symbol parameter value unit t stg storage temperature (v cc off) ?55 to 150 c t sld (1) 1. reflow at peak temperature of 260 c. the time above 255 c must not exceed 30 seconds. lead solder temperature for 10 seconds 260 c v io input or output voltage ?0.3 to v cc +0.3 v v cc /v bat supply voltage ?0.3 to 6.0 v i o output current 20 ma p d power dissipation 320 mw
stm690a/692a/703/704/802/805/81 7/818/819 dc and ac parameters doc id 10522 rev 9 31/42 5 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 6: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 39. e to e con propagation delay test circuit 1. c l includes load capacitance and scope probe capacitance. table 6. operating and ac measurement conditions parameter stm690a/692a/703/704/802/805/ 817/818/819 unit v cc /v bat supply voltage 1.0 to 5.5 v ambient operating temperature (t a ) ?40 to 85 c input rise and fall times 5ns input pulse voltages 0.2 to 0.8v cc v input and output timing ref. voltages 0.3 to 0.7v cc v ai0 88 54 v bat e con v cc v cc 3.6v 50pf c l (1) 25 equivalent source impedance 50 cable 50 50 stmxxx gnd e
dc and ac parameters stm690a/69 2a/703/704/802/ 805/817/818/819 32/42 doc id 10522 rev 9 figure 40. ac testing input/output waveforms figure 41. mr timing waveform 1. rst for stm805. figure 42. watchdog timing ai0256 8 0.8v cc 0.2v cc 0.7v cc 0.3v cc ai07 83 7 a rst (1) mr t mlrl t rec t mlmh ai07 8 91 rst wdi v cc t rec t wd
stm690a/692a/703/704/802/805/81 7/818/819 dc and ac parameters doc id 10522 rev 9 33/42 table 7. dc and ac characteristics sym alter- native description test condition (1) min typ max unit v cc , v bat (2) operating voltage t a = ?40 to +85 c 1.2 (3) 5.5 v i cc v cc supply current excluding i out (v cc < 5.5 v) 25 60 a v cc supply current in battery backup mode excluding i out (v bat = 2.3 v, v cc = 2.0 v, mr = v cc ) 25 35 a i bat (4) v bat supply current in battery backup mode excluding i out (v bat = 3.6 v) 0.4 1.0 a v out1 v out voltage (active) i out1 = 5 ma (5) v cc ? 0.03 v cc ? 0.015 v i out1 = 75 ma v cc ? 0.3 v cc ? 0.15 v i out1 = 250 a, v cc > 2.5 v (5) v cc ? 0.0015 v cc ? 0.0006 v v out2 v out voltage (battery backup) i out2 = 250 a, v bat = 2.3 v v bat ? 0.1 v bat ? 0.034 v i out2 = 1 ma, v bat = 2.3 v v bat ? 0.14 v v cc to v out on-resistance 34 v bat to v out on-resistance 100 i li input leakage current (mr ) 4.5 v < v cc < 5.5 v 75 125 300 a input leakage current (pfi) 0 v < v in < v cc ?25 2 +25 na input leakage current (wdi) (6) wdi = v cc , time average 120 160 a wdi = gnd, time average ?20 ?15 a v ih input high voltage (mr ) 4.5 v < v cc < 5.5 v 2.0 v v ih input high voltage (wdi) v rst (max) < v cc < 5.5 v 0.7v cc v v il input low voltage (mr ) 4.5 v < v cc < 5.5 v 0.8 v v il input low voltage (wdi) v rst (max) < v cc < 5.5 v 0.3v cc v v ol output low voltage (pfo , rst , rst) v cc = v rst (max), i sink = 3.2 ma 0.3 v output low voltage (e con ) v cc = v rst (max), i out = 1.6 ma, e = 0 v 0.2v cc v v ol output low voltage (rst ) i sink = 50 a, v cc = 1.0 v, v bat = v cc , t a = 0c to 85c 0.3 v i sink = 100 a, v cc = 1.2 v, v bat = v cc 0.3 v
dc and ac parameters stm690a/69 2a/703/704/802/ 805/817/818/819 34/42 doc id 10522 rev 9 v oh output high voltage (rst , rst) i source = 1 ma v cc = v rst (max) 2.4 v output high voltage (e con ) v cc = v rst (max), i out = 1.6 ma, e = v cc 0.8v cc v output high voltage (pfo ) i source = 75 a, v cc = v rst (max) 0.8v cc v v oh output high voltage i source = 4 a, v cc = 1.1 v, v bat = v cc , t a = 0c to 85c 0.8 v i source = 4 a, v cc = 1.2 v, v bat = v cc 0.9 v v ohb v oh battery backup (rst , rst) i source = 100 a, v cc = 0, v bat = 2.8 v 0.8v bat v v oh battery backup (e con ) i source = 75 a, v cc = 0, v bat = 2.8 v 0.8v bat v power-fail comparator (n ot available on stm818) v pfi pfi input threshold pfi falling (v cc = 5 v) all other versions 1.20 1.25 1.30 v stm802 1.225 1.250 1.275 v t pfd pfi to pfo propagation delay 2s i sc pfo output short to gnd current v cc = 5 v, v pfo = 0 v 0.1 0.75 2.0 ma battery switchover vso battery backup switchover voltage (7)(8) (v cc < v bat & v cc < v rst ) power-down v rst > v bat v bat v v rst < v bat v rst v power-up v rst > v bat v bat v v rst < v bat v rst v hysteresis 40 mv reset thresholds v rst reset threshold (9) stm690a/703, stm8xxl 4.50 4.65 4.75 v stm692a/704, stm8xxm 4.25 4.40 4.50 v reset threshold hysteresis 25 mv v cc to rst delay (from v rst , v cc falling at 10 v/ms) stm817/818/819 100 s table 7. dc and ac characteristics (continued) sym alter- native description test condition (1) min typ max unit
stm690a/692a/703/704/802/805/81 7/818/819 dc and ac parameters doc id 10522 rev 9 35/42 t rec rst pulse width 140 200 280 ms push-button reset input (stm703/704/819) t mlmh t mr mr pulse width stm703/704 150 ns stm819 1 s t mlmr t mrd mr to rst output delay stm703/704 250 ns stm819 120 ns mr glitch immunity stm819 100 ns mr pull-up resistor mr = 0 v, v cc = 5 v 45 63 85 k watchdog timer (not available on stm703/704/819) t wd watchdog timeout period v rst (max) < v cc < 5.5 v 1.12 1.60 2.24 s wdi pulse width v rst (max) < v cc < 5.5 v 50 ns chip-enable gating (stm818 only) e to e con resistance v cc = v rst (max) 40 150 e to e con propagation delay 4.5 v < v cc < 5.5 v 2 7 ns reset to e con high delay (power-down) 15 s e con short circuit current v cc = 5 v, disable mode, e = logic high, e con = 0 v 0.1 0.75 2.0 ma 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 4.75 v to 5.5 v for ?l? versions; v cc = 4.5 v to 5.5 v for ?m? versions; and v bat = 2.8 v (except where noted). 2. v cc supply current , logic input leakage , watchdog functionality , push - button reset functionality, pfi functionality, state of rst and rst tested at v bat = 3.6 v, and v cc = 5.5 v. the state of rst or rst and pfo is tested at v cc = v cc (min). either v cc or v bat can go to 0 v if the other is greater than 2.0 v. 3. v cc (min) = 1.0 v for t a = 0 c to +85 c. 4. tested at v bat = 3.6 v, v cc = 3.5 v and 0 v. 5. guaranteed by design. 6. wdi input is designed to be driven by a three-state output device. to float wdi, the ?high impedance mode? of the output device must have a maximum leakage current of 10 a and a maximum output capacitance of 200 pf. the output device must also be able to source and sink at least 200 a when active. 7. when v bat > v cc > v rst , v out remains connected to v cc until v cc drops below v rst . 8. when v rst > v cc > v bat , v out remains connected to v cc until v cc drops below the battery voltage (v bat ) ? 75 mv. 9. for v cc falling. table 7. dc and ac characteristics (continued) sym alter- native description test condition (1) min typ max unit
package mechanical data stm690a/ 692a/703/704/802/ 805/817/818/819 36/42 doc id 10522 rev 9 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
stm690a/692a/703/704/802/805/817/ 818/819 package mechanical data doc id 10522 rev 9 37/42 figure 43. so8 - 8-lead plastic small outline, 150 mils body width, package mechanical drawing note: drawing is not to scale. s o-a e 8 ddd b e a d c l a1 1 h a2 table 8. so8 - 8-lead plastic small out line, 150 mils body width, package mechanical data symbol mm inches typ min max typ min max a - 1.35 1.75 - 0.053 0.069 a1 - 0.10 0.25 - 0.004 0.010 b - 0.33 0.51 - 0.013 0.020 c - 0.19 0.25 - 0.007 0.010 d - 4.80 5.00 - 0.189 0.197 ddd - - 0.10 - - 0.004 e - 3.80 4.00 - 0.150 0.157 e 1.27 - - 0.050 - - h - 5.80 6.20 - 0.228 0.244 h - 0.25 0.50 - 0.010 0.020 l - 0.40 0.90 - 0.016 0.035 - 0 8 - 0 8 n8 8
package mechanical data stm690a/ 692a/703/704/802/ 805/817/818/819 38/42 doc id 10522 rev 9 figure 44. tssop8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, outline note: drawing is not to scale. t ss op 8 bm 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1 table 9. tssop8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data symbol mm inches typ min max typ min max a - - 1.10 - - 0.043 a1 - 0.05 0.15 - 0.002 0.006 a2 0.85 0.75 0.95 0.034 0.030 0.037 b - 0.25 0.40 - 0.010 0.016 c - 0.13 0.23 - 0.005 0.009 cp - - 0.10 - - 0.004 d 3.00 2.90 3.10 0.118 0.114 0.122 e 0.65 - - 0.026 - - e 4.90 4.65 5.15 0.193 0.183 0.203 e1 3.00 2.90 3.10 0.118 0.114 0.122 l 0.55 0.40 0.70 0.022 0.016 0.030 l1 0.95 - - 0.037 - - -06 - 0 6 n8 8
stm690a/692a/703/704/802/805/ 817/818/819 part numbering doc id 10522 rev 9 39/42 7 part numbering table 10. ordering information scheme for other options or for more information on any aspect of this device, please contact the st sales office nearest you. example: stm690a m 6 e device type stm690a/692a/703/704/802/805/817/818/819 threshold voltage stm690a, stm703: blank: v rst = 4.50 v to 4.75 v stm692a, stm704: blank: v rst = 4.25 v to 4.50 v stm8xx: l: v rst = 4.50 v to 4.75 v m: v rst = 4.25 v to 4.50 v package m = so8 ds (1) = tssop 1. contact local st sales ofice for availability temperature range 6: ?40 c to 85 c shipping method e = ecopack ? package, tubes f = ecopack ? package, tape & reel
part numbering stm690a/692a /703/704/802/80 5/817/818/819 40/42 doc id 10522 rev 9 table 11. marking description part number reset threshold package topside marking stm690a 4.65 v so8 690a stm692a 4.40 v so8 692a stm703 4.65 v so8 703 stm704 4.40 v so8 704 stm802l 4.65 v so8 802l stm802m 4.40 v so8 802m stm805l 4.65 v so8 805l stm817l 4.65 v so8 817l tssop8 stm817m 4.40 v so8 817m tssop8 stm818l 4.65 v so8 818l tssop8 stm818m 4.40 v so8 818m tssop8 stm819l 4.65 v so8 819l tssop8 stm819m 4.40 v so8 819m tssop8
stm690a/692a/703/704/802/805/ 817/818/819 revi sion history doc id 10522 rev 9 41/42 8 revision history table 12. document revision history date revision changes oct-2003 1 initial release. 31-oct-2003 1.1 update dc characteristics ( table 7 ). 22-dec-2003 2 reformatted; updated characteristics (cover page, figure 2 , 3 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 16 , table 3 , 4 , 7 , 9 , 11 ). 16-jan-2004 2.1 add typical characteristics ( figure 18 , 19 , 21 , 22 , 24 , 25 , 26 , 27 , 28 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 ). 08-apr-2004 2.2 update characteristics ( figure 12 , 22 , 28 , 32 , 33 , 34 , 37 ; table 1 , 7 ). 25-may-2004 3 remove references to ?open drain? (cover page, 4 , 7 ; ta ble 2 ); update characteristics ( ta ble 3 , 7 ). 05-jul-2004 4 update package availability, pin description; promote document (cover page, figure 13 , 14 ; table 3 , 7 , 10 ). 29-sep-2004 5 clarify root part numbers, pin descriptions ( figure 10 , 12 , 39 ; table 7 , 10 ). 01-mar-2005 6 update characteristics ( figure 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 ) 20-jan-2006 7 correct marking, update lead-free text ( table 10 , 11 ) 21-oct-2008 8 reformatted, minor text changes; updated table 3 , 4 , 7 , 10 , figure 9 , 10 , 11 , 12 , 16 , 39 , section 6: package mechanical data . 20-nov-2009 9 updated text in section 6 , ta ble 5 .
stm690a/692a/703/704 /802/805/817/818/819 42/42 doc id 10522 rev 9 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military , air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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